The present invention relates in general to computer devices, and, more particularly, to a system and method for interfacing software and hardware.
Many electro-mechanical systems use processors to perform operations. Prior to implementation, these processors are tested and debugged to ensure they perform their designed functions. Logic simulation with architecture level visibility into the processors allows internal signals to be probed, logic simulation to check logic levels, and cycle/phase accuracy to be confirmed. If the logic simulation uses device timing, they can perform full timing verifications of the system.
During early stages of processor design, hardware and software comparisons may be done in the system. Generally, these systems have software debug capability under simulation. Additionally, capability to control logic simulation with a debug abstraction, such as break points, single stepping, or interrupt, is desirable. However, these systems result in a significant amount of redesign and redundancy. These considerations particularly are costly when the processor design is in its infancy.
Previous attempts to provide these tests include digital circuitry in the processors that allow debug software to interface with the processors. Further, testability structures may be built into the design system to assess software debug operations. However, these testability structures are tailored to the various design modules, which have different levels of accuracy, such as functions, timing, or memory. These additional testability structures and circuitry increase space and cost considerations in designing the processors.
From the foregoing, it may be appreciated that a need has arisen for a method for interfacing hardware and software without structures in the design system and additional circuitry on the processors. In accordance with the present invention, a system and method for interfacing hardware and software is provided that substantially eliminates and reduces the disadvantages and problems associated with conventional test interface operations.
In accordance with one embodiment of the present invention, a method of for interfacing hardware and software in a simulation system comprises initializing a cell by resetting the cell and having a model access and control hub store configuration data of blocks on the cell to a shared memory, spawning a debugger, the debugger coupled to the model access and control hub by an interprocess communication device including the shared memory, loading the configuration data to the debugger from the shared memory, formulating and sending a command from the debugger to the model access and control hub via the shared memory in the cell, receiving a signal at the model access and control hub from the blocks at the completion of the executing step, and transmitting the signal to the debugger from the model access and control hub and executing the command on the blocks control hub via the shared memory.
A technical advantage of the present invention is that a system and method for interfacing software and hardware in a simulation system is described. Another technical advantage of the present invention is that it is modular and extendable, and it enables co-simulation over heterogenous, multiprocessor design systems. Another technical advantage of the present invention is that a modular interface is provided that maintains transparency of information exchange between interacting modules of a design system. Another technical advantage is that it allows interfacing between complex design systems with heterogenous processors, each with their own clock rate. Another technical advantage is that a software debugger interface is provided that allows direct access to control and observe processors, and their associated memory modules, without consuming or disturbing the circuitry outside the processors. Another technical advantage of the present invention is that an interface is provided that does not require the existence of any testability structures in the design system to assist in software debug operations. Another technical advantage of the present invention is that a system is provided that is modular and extendable to any number of processors regardless of type. Another technical advantage is that a software and hardware interface is provided to allow logic simulation of designs where the various design modules are simulating at different levels, such as function, timing, or memory. Another technical advantage of the present invention is that a software and hardware interface is provided that allows debug operations to occur in a rapid manner.